· Verilog has clearer distinction between register and nets. Nets are used to model electrical connections, while registers hold values and act as memory elements.
· Nets have strengths and delay properties which emphasize their physical aspects. The delay may consist of up to 9 values; a different value may be assigned for each transition 0, 1 or z and for each minimum, typical and maximum case. Such a delay attached to a net is added to the delay of each assigned statement. The net types include wire,tri,wand,triand,wor,trior,tri0,tril(resistive),supply0,supply1 and trireg (with charge storage).
· Primitive gates include and, or, xor & not.
· Verilog is concise and easier to learn as compared with VHDL. Unlike Verilog, VHDL is extremely verbose, which means it requires many characters to say something simple. This is why there are many different ways of saying the same thing in VHDL which makes it complicated and confusing. VHDL is exact in nature and difficult to learn. Verilog is deemed quicker to code and debug as compared with VHDL.
· Unlike VHDL, Verilog has fork-join block. This construct lets you have nested parallel sequential blocks inside each other. This is a very powerful feature which is sometimes termed as 'multi-threading'. You cannot have this feature in VHDL unless you use explicit synchronizations between two different processes.
· Unlike VHDL, Verilog is not a strongly typed language and this is why a 32-bit bus may be connected with and 8-bit bus by just padding the extra bits. Verilog does not require additional coding to convert from one data type to another data type like integer to bit-vector. So it does not have to pay the performance penalty caused by strong type checking and the designer productivity is also expected to be high in this case.
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