Verilog vs VHDL :Superior Features of VHDL

 Superior Features of  VHDL:

·        Unlike Verilog, the concept of packages in VHDL, library management and separate compilation makes it an ideal candidate for higher level system modeling. There is no concept of packages in Verilog. Functions and procedures used within a module have to be defined inside the same module and thus they cannot be shared by different modules. However, the concept of package in Verilog may be emulated by declaring and instantiating a fictitious module with functions and procedures. Verilog, unlike VHDL, does not support library management and separate compilation. This is why; Verilog requires all modules being used in same simulation must be written in the same file.

·         Unlike VHDL, Verilog types are very restrictive and are specific to IC modeling (wire, supply0, supply1 etc.). Many abstract data types may be defined in VHDL while Verilog data types are predefined.

·         Unlike VHDL, Verilog has no concept of configurations and it lacks generics and textio.

·         Unlike VHDL, Verilog has no access types.

·         Unlike Verilog, VHDL has extensive type checking feature; this is why many errors may be caught before synthesis and simulation.

·         VHDL provides more details in assignment and application of individual cells and signals within FPGA, but this requires a much better understanding of the FPGA. As compared with VHDL, Verilog despite being much easier to learn is neither efficient in use of available cells nor does it necessarily generate the fastest running implementation from the components available in FPGA.

·         Unlike Verilog, the verbosity of VHDL makes it self-documenting.

·         VHDL semantics are unambiguous and VHDL based design may easily be ported from one tool to another. This is why race conditions are never a concern for VHDL users. Simulation semantics in Verilog are more ambiguous than in VHDL. Though this ambiguity in Verilog semantics, gives designer more flexibility in applying optimization but it can also (and often does) result in race conditions if careful coding guidelines are not followed. It is highly probable that a Verilog based design generates different results on different vendors' tools or on different releases of the same vendor's tool.  

·         The advantage of strong typing in VHDL is that the potential bugs in the design may be identified as early in a verification process as possible. Many problems that strong typing uncover are identified during analysis/compilation of the source code.