FPGA General Overview

General  Overview

There are several families of FPGAs available from different semiconductor companies. These device families slightly differ in their architecture and feature set, however most of them follow a common approach: A regular, flexible, programmable architecture of Configurable Logic Blocks (CLBs), surrounded by a perimeter of programmable Input/Output Blocks (IOBs). These functional elements are interconnected by a powerful hierarchy of versatile routing channels.

The following paragraphs describe the architecture implemented by Xilinx Spartan-II FPGAs, a device family launched in mid 2000, which is typically used in high-volume applications where the versatility of a fast programmable solution adds benefits.

The user-programmable gate array, shown in Figure 15, is composed of five major configurable elements:

IOBs provide the interface between the package pins and the internal logic CLBs provide the functional elements for constructing most logic Dedicated BlockRAM memories of 4096 bits each

Clock DLLs for clock-distribution delay compensation and clock domain control

Versatile multi-level interconnect structure   

As can be seen in Figure 15, the CLBs form the central logic structure with easy access to all support and routing structures. The IOBs are located around all the logic and memory elements for easy and quick routing of signals on and off the chip.

Figure 15: Basic Spartan-II Block Diagram

Values stored in static memory cells control all the configurable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device.

Figure 16: FPGA Slice

Configurable Logic Block
The basic building block of the CLBs is the logic cell (LC). An LC includes a 4-
input function generator, carry logic, and a storage element. The output from the
function generator in each LC drives both the CLB output and the D input of the
flip-flop. Each CLB contains four LCs, organized in two similar slices; a single slice
is shown in Figure 16.
In addition to the four basic LCs, the CLBs contains logic that combines function
generators to provide functions of five or six inputs. Consequently, when
estimating the number of system gates provided by a given device, each CLB
counts as 4.5 LCs.
Look-Up Tables
The function generators are implemented as 4-input look-up tables (LUTs). In
addition to operating as a function generator, each LUT can provide a 16x1-bit
synchronous RAM. Furthermore, the two LUTs within a slice can be combined to
create a 16x2-bit or 32x1-bit synchronous RAM, or a 16x1-bit dual-port
synchronous RAM.
The LUT can also provide a 16-bit shift register that is ideal for capturing high-
speed or burst-mode data. This mode can also be used to store data in
applications such as Digital Signal Processing. See Figure 17 for details on slice
configuration.